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MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
Dual 3.3V PLL Clock Generator
The MPC980 is a 3.3V dual PLL clock generator targeted for high end PentiumTM and PowerPCTM 603/604 personal computers. The MPC980 synthesizes processor as well as PCI clocks from a 14.31818MHz external crystal. In addition the device provides two buffered outputs of the 14.31818MHz crystal as well as a 40MHz SCSI clock, a 24MHz floppy clock and a 12MHz keyboard clock. One of the buffered 14.31818MHz outputs can be configured to provide a 16MHz output rather than the second copy of the 14.31818MHz output.
MPC980
DUAL 3.3V PLL CLOCK GENERATOR
* Provides Processor and System Clocks for PentiumTM Designs * Provides Processor and System Clocks for PowerPCTM 603/604
Designs
* Two Fully Integrated Phase-Locked Loops * Cycle-to-Cycle Jitter of 150ps * Operates from 3.3V Supply * 52-Lead LQFP Packaging
The processor clock outputs of the MPC980 can be programmed to provide 50, 60 or 66MHz. Under all processor output frequencies the PCI clock outputs will be equal to one half the processor clock outputs. The PCI outputs will run synchronously to the processor clock outputs. There are a total of ten output clocks which can be split into a group of four and a group of six. Either group can be configured as processor or PCI clocks. Each of the outputs can drive two series terminated transmission lines allowing for the driving of up to twelve independent processor loads and eight PCI clock loads. A pin selectable option is available to delay the PCI clock outputs relative to the processor clocks. The amount of delay is a function of the processor clock frequency and varies from 2ns to 6ns.
FA SUFFIX 52-LEAD LQFP PACKAGE CASE 848D-03
The output jitter of the the PLL at 66MHz output is 150ps peak-to-peak, cycle-to-cycle (the worst case deviation of the clock period is guaranteed to be less than 150ps). The skews between one processor clock and any other processor clock (or one PCI clock to any other PCI clock) is 350ps. The worst case skew between the processor clocks and the PCI clocks is 500ps. An output enable pin is provided to tristate all of the outputs for board level test. In addition a testing mode is provided to allow for the bypass of the PLL's for board level functional debug.
Pentium is a trademark of Intel Corporation. PowerPC is a trademark of International Business Machines Corporation. 1/98
(c) Motorola, Inc. 1998
1
REV 2
MPC980
fsel2 Dly_PCI fsel0:1 TCLK_Sel 14.31818MHz Xtal Osc 2 Processor Clock PLL Test Mode /2 /2//4 /4 0 1 TCLK 16M_Sel 16MHz System Clock PLL OE 12MHz 24MHz 40MHz Q12M Q24M Q40M 0 1 Q14_16M Q14.3M 4 QPCI0:3 4 2
QP0:3 QP4:5_QPCI4:5
Figure 1. Logic Diagram
Table 1. Pin Descriptions
Pin 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 Label VCCA TCLK_Sel TCLK Xtal1 Xtal2 GND DLY_PCI VCCI fsel0 fsel1 fsel2 VCCA GNDA 16M_SEL Q14_16M GND0 VCC0 Q14M GND0 QP0 VCC0 QP1 GND0 QP2 VCC0 50K 50K 50K 50K 50K 50K None None None Description Analog VCC for System PLL Use Filter (Note 1.) Sel Ext'l TCLK or Internal Xtal Ref External LVCMOS Ref Signal Xtal Pin 1 Xtal Pin 2 System Ground Input Sets QP & QPI Relationship
(See Function Table 2 on page 3.)
Pin 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51
Label GNDI VCCO QP3 GND0 GND0 QP4_PCI4 VCC0 QP5_PCI5 GND0 GND0 QPCI3 VCCO QPCI2 GND0 VCCI GND0 QPCI1 VCC0 QPCI0 GND0 QM12 VCC0 Q40M GND0 Q24M OE
Description System Ground Input VCC in for the CMOS Outputs CMOS Output QP3 System Ground Input System Ground Input CMOS Output QP4_PCI4 VCC in for the CMOS Outputs CMOS Output QP5_PCI5 System Ground Input System Ground Input CMOS Output QPCI3 VCC in for the CMOS Outputs CMOS Output QPCI2 System Ground Input VCC for Internal Core Logic System Ground Input CMOS Output QPCI1 VCC in for the CMOS Outputs CMOS Output QPCI0 System Ground Input CMOS Output QM12 VCC in for the CMOS Outputs CMOS Output Q40M System Ground Input CMOS Output Q24M
VCC Pin for Internal Circuits Least Bit for QP/QPI Output Funct
(See Function Table 1 on page 3.)
Most Bit for QP/QPI Output Function
(See Function Table 1 on page 3.)
Selection of QP/QPI Output Funct
(See Function Table 4 on page 3.)
Analog VCC Proc'ssr PLL Use Filter
(Note 1.)
System Ground Input Selects 16MHz / 14MHz for Q14_16M Output Output for 16MHz / 14MHz Xtal Osc System Ground Input VCC in for the CMOS Outputs CMOS Output for 14.3MHz Xtal Osc System Ground Input CMOS Output QP0 VCC in for the CMOS Outputs CMOS Output QP1 System Ground Input CMOS Output QP2 VCC in for the CMOS Outputs
50K
Select Output State
(See Function Table 1 on page 3.)
52 GND0 System Ground Input 1. The filter recommended for the analog power pins is found in Figure 3 in the Applications Information section on page 5.
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MPC980
QP5_PCI5 QP4_PCI4
QPCI2
QPCI3
GND0
GND0
GND0
GND0
GND0
VCC0
VCC0
39 VCCI GND0 QPCI1 VCC0 QPCI0 GND0 Q12M VCC0 Q40M GND0 Q24M OE GNDA 40 41 42 43 44 45 46 47 48 49 50 51 52 1
38
37
36
35
34
33
32
31
30
29
28
VCC0 27 26 25 24 23 22 21 GNDI VCC0 QP2 GND0 QP1 VCC0 QP0 GND0 Q14M VCC0 GND0 Q14_16M 16M_Sel 20 19 18 17 16 15 14 13 GNDA Q24M Hi Z 24 24 24 TCLK/4
MPC980
2
3
4
5
6
7
8
9
10
11
VCCI
VCCA
TCLK_Sel
Dly_PCI
Figure 2. 52-Lead Pinout (Top View)
Function Table 1
OE 0 1 1 1 1 fsel0 X 0 0 1 1 fsel1 X 0 1 0 1 QP High Impedance 50MHz 60MHz 66MHz TCLK/2 QPCI High Impedance 25MHz 30MHz 33MHz TCLK/4 Q14M Hi Z 14.31818 14.31818 14.31818 TCLK Q16M Hi Z 16 16 16 TCLK/6 Q12M Hi Z 12 12 12 TCLK/8 Q40M Hi Z 40 40 40 TCLK/2
Function Table 2
Dly_PCI 0 1 QP/QPCI Relationship Synchronous Processor & PCI Clocks PCI Clocks Lag Processor Clocks
Function Table 4
fsel2 0 1 QP/QPCI Output Configuration 6 Processor and 4 PCI Clocks 4 Processor and 6 PCI Clocks
Function Table 3
TCLK_Sel 0 1 PLL Input Reference Crystal Oscillator TCLK
Function Table 5
16M_Sel 0 1 Q14_16M Output Configuration 14.31818MHz to Q14_16M Out 16MHz to Q14_16M Out
ECLinPS and ECLinPS Lite DL140 -- Rev 3
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VCCA
Xtal1
TCLK
Xtal2
GND
fsel0
fsel1
fsel2
QP3 12
MOTOROLA
MPC980
DC CHARACTERISTICS (TA = 0 to 70C)
Symbol VCC VIL VIH VOH VOL CIN CPD ICC Characteristic Power Supply Voltage Input LOW Voltage Input HIGH Voltage Output HIGH Voltage Output LOW Voltage Input Capacitance Power Dissipation Capacitance Quiescent Supply Current 25 190 0.7VCC VCC -0.4 0.4 4.5 Min 3.3-5% Typ 3.3 Max 3.3+5% 0.3VCC VCC Unit V V V V V pF pF mA -20mA (Note 1.) +20mA (Note 1.) Condition
ICCA PLL Supply Current 20 mA 1. Output can drive two series terminated 50 transmission lines or a single 50 line terminated 50 into VCC/2.
AC CHARACTERISTICS (TA = 0 to 70C, VCC = 3.3V 5%)
Symbol fXtal fmax tdc tjitter Characteristic Input Crystal Frequency Maximum Output Frequency Output Duty Cycle Cycle-to-Cycle Jitter (Peak-to-Peak) Output-to-Output Skew 66/33MHz 60/30MHz 50/25MHz QP to QP QPCI to QPCI QP to QPCI QP to QPCI 2 0.05 1 4fQP QP QPCI tCYCLE/2 -1000 tCYCLE/2 500 Min Typ 14.31818 66 33 tCYCLE/2 +1000 150 200 250 350 350 500 1 4fQP Max Unit MHz MHz ps ps Condition
tskew
ps
Rising Edges Only; Dly_PCI = 0 Dly_PCI = 1 1.0 to 1.8V
tdelay tr, tf tLOCK tPZL, tPZH tPLZ, tPHZ
Time Delay Output Rise/Fall Time PLL Lock Time Output Enable Time Output Disable Time
)1
ns ns ms ns ns
0.8 10
3 4
10 11
50 to VCC/2 50 to VCC/2
APPLICATIONS INFORMATION
Using the On-Board Crystal Oscillator The MPC980 features an on-board crystal Oscillator to allow for seed clock generation as well as final distribution. The on-board Oscillator is completely self contained so that the only external component required is the crystal. As the Oscillator is somewhat sensitive to loading on its inputs the user is advised to mount the crystal as close to the MPC980 as possible to avoid any board level parasitics. To facilitate co-location surface mount crystals are recommended, but not required. The Oscillator circuit is a series resonant circuit as opposed to the more common parallel resonant circuit, this eliminates the need for large on-board capacitors. Because the design is a series resonant design for the optimum frequency accuracy a series resonant crystal should be used (see specification table below). Unfortunately most off the shelf crystals are characterized in a parallel resonant mode. However a parallel resonant crystal is physically no different than a series resonant crystal, a parallel resonant crystal is simply a crystal which has been characterized in its parallel
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resonant mode. Therefore in the majority of cases a parallel specified crystal can be used with the MPC980 with just a minor frequency error due to the actual series resonant frequency of the parallel resonant specified crystal. Typically a parallel specified crystal used in a series resonant mode will exhibit an Oscillatory frequency a few hundred ppm lower than the specified value. For most processor implementa- tions a few hundred ppm translates into kHz inaccuracies, a level which does not represent a major issue. Table 2. Crystal Specifications
Parameter Crystal Cut Resonance Frequency Tolerance Frequency/Temperature Stability Operating Range Shunt Capacitance Equivalent Series Resistance (ESR) Correlation Drive Level Aging Value Fundamental at Cut Series Resonance* 75ppm at 25C 150ppm 0 to 70C 0 to 70C 5-7pF 50 to 80 Max 100W 5ppm/Yr (First 3 Years) PLL_VCC 22F MPC980 VCCA Pins 1 & 12 VCC 0.01F 0.01F RS=5-15 3.3V
noise whose spectral content is above 20KHz. As the noise frequency crosses the series resonant point of an individual capacitor it's overall impedance begins to look inductive and thus increases with increasing frequency. The parallel capacitor combination shown ensures that a low impedance path to ground exists for frequencies well above the bandwidth of the PLL. It is recommended that the user start with an 8-10 resistor to avoid potential VCC drop problems and only move to the higher value resistors when a higher level of attenuation is shown to be needed.
* See accompanying text for series versus parallel resonant discussion.
Figure 3. Power Supply Filter Although the MPC980 has several design features to minimize the susceptibility to power supply noise (isolated power and grounds and fully differential PLL) there still may be applications in which overall performance is being degraded due to system power supply noise. The power supply filter schemes discussed in this section should be adequate to eliminate power supply noise related problems in most designs. Component Reliability Analysis Information All inputs and outputs of the MPC980 clock generator are LVCMOS and are not 5V tolerant. The quiescent current is 190mA maximum, so the maximum quiescent power is (190mA) x (3.465V max-VCC) = 658.35mW. Total maximum power must include the dynamic power of the outputs. Dynamic Power/Output = [Logic Swing Out (volts)] x [VCC (volts)] x [Freq (MHz)] x [Cl + Cp (pF)] where CL = Load Capacitance CP = Output Power Dissipation Capacitance The MPC980 is packaged in a 52-lead LQFP to optimize board space and power supply distribution. The LQFP package occupies a 12mm x 12mm space on the PCB. The 52-Pin LQFP package has a JA of 64 to 74C/W in still air and a JA of 42 to 52C/W in 500lfpm of moving air. The maximum chip temperature for the device is 140C. The device component count is: NPN Bipolar devices 2,238; NMOS devices 1,313; PMOS devices 281.
Power Supply Filtering The MPC980 is a mixed analog/digital product and as such it exhibits some sensitivities that would not necessarily be seen on a fully digital product. Analog circuitry is naturally susceptible to random noise, especially if this noise is seen on the power supply pins. The MPC980 provides separate power supplies for the output buffers (VCCO) and the phase-locked loop (VCCA) of the device. The purpose of this design technique is to try and isolate the high switching noise digital outputs from the relatively sensitive internal analog phase-locked loop. In a controlled environment such as an evaluation board this level of isolation is sufficient. However, in a digital system environment where it is more difficult to minimize noise on the power supplies a second level of isolation may be required. The simplest form of isolation is a power supply filter on the VCCA pin for the MPC980. Figure 3 illustrates a typical power supply filter scheme. The MPC980 is most susceptible to noise with spectral content in the 1KHz to 1MHz range. Therefore the filter should be designed to target this range. The key parameter that needs to be met in the final filter design is the DC voltage drop that will be seen between the VCC supply and the VCCA pin of the MPC980. From the data sheet the IVCCA current (the current sourced per VCCA pin) is typically 15mA (20mA maximum), assuming that a minimum of 3.0V must be maintained on the VCCA pin very little DC voltage drop can be tolerated when a 3.3V VCC supply is used. The resistor shown in Figure 3 must have a resistance of 10-15 to meet the voltage drop criteria. The RC filter pictured will provide a broadband filter with approximately 100:1 attenuation for
ECLinPS and ECLinPS Lite DL140 -- Rev 3
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MOTOROLA
MPC980
OUTLINE DIMENSIONS
FA SUFFIX PLASTIC LQFP PACKAGE CASE 848D-03 ISSUE D
C L AB
4X 4X 13 TIPS
-X- X=L, M, N
G
0.20 (0.008) H L-M N
0.20 (0.008) T L-M N
AB VIEW Y
52 1
40 39 PLATING
F
BASE METAL
3X
VIEW Y -M- B V
-L-
J
0.13 (0.005) B1
13 14 26 27
V1
SECTION AB-AB
ROTATED 90_ CLOCKWISE
A1 S1 A S
-N-
C -H- -T-
SEATING PLANE
4X
q2
0.10 (0.004) T
NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DATUM PLANE -H- IS LOCATED AT BOTTOM OF LEAD AND IS COINCIDENT WITH THE LEAD WHERE THE LEAD EXITS THE PLASTIC BODY AT THE BOTTOM OF THE PARTING LINE. 4. DATUMS -L-, -M- AND -N- TO BE DETERMINED AT DATUM PLANE -H-. 5. DIMENSIONS S AND V TO BE DETERMINED AT SEATING PLANE -T-. 6. DIMENSIONS A AND B DO NOT INCLUDE MOLD PROTRUSION. ALLOWABLE PROTRUSION IS 0.25 (0.010) PER SIDE. DIMENSIONS A AND B DO INCLUDE MOLD MISMATCH AND ARE DETERMINED AT DATUM PLANE -H-. 7. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. DAMBAR PROTRUSION SHALL NOT CAUSE THE LEAD WIDTH TO EXCEED 0.46 (0.018). MINIMUM SPACE BETWEEN PROTRUSION AND ADJACENT LEAD OR PROTRUSION 0.07 (0.003). MILLIMETERS MIN MAX 10.00 BSC 5.00 BSC 10.00 BSC 5.00 BSC --- 1.70 0.05 0.20 1.30 1.50 0.20 0.40 0.45 0.75 0.22 0.35 0.65 BSC 0.07 0.20 0.50 REF 0.08 0.20 12.00 BSC 6.00 BSC 0.09 0.16 12.00 BSC 6.00 BSC 0.20 REF 1.00 REF 0_ 7_ --- 0_ 12 _ REF 12 _ REF INCHES MIN MAX 0.394 BSC 0.197 BSC 0.394 BSC 0.197 BSC --- 0.067 0.002 0.008 0.051 0.059 0.008 0.016 0.018 0.030 0.009 0.014 0.026 BSC 0.003 0.008 0.020 REF 0.003 0.008 0.472 BSC 0.236 BSC 0.004 0.006 0.472 BSC 0.236 BSC 0.008 REF 0.039 REF 0_ 7_ --- 0_ 12 _ REF 12 _ REF
4X
q3
VIEW AA
0.05 (0.002)
S
W
q1
C2
2X R
R1
0.25 (0.010)
q
GAGE PLANE
K C1 E VIEW AA Z
DIM A A1 B B1 C C1 C2 D E F G J K R1 S S1 U V V1 W Z 1 2 3
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CCCC EEEE CCCC EEEE
M
U
D T L-M
S
N
S
ECLinPS and ECLinPS Lite DL140 -- Rev 3
MPC980
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ECLinPS and ECLinPS Lite DL140 -- Rev 3 7
MPC980/D MOTOROLA

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